DESIGN OF A FULL ADDER CIRCUIT

ABSTRACT
In this project, two high performance adder cells are proposed. We simulated these two full adder cells using HSPICE in 0.18 µm, CMOS technology and at 25-degree of temperature with supply voltage range from 0.5v to 3.3v with 0.1v steps. Results show that the proposed adders operate successfully when connected to a 0.5 V power supply. The two adders differ in the technology applied to their gates. While the first circuit applies CMOS technology, the second and optimal one uses Past Transistor Logic. The average power dissipation of the optimum is 4.3269*10-7 watt, which illustrates an amazing performance.

CHAPTER ONE

INTRODUCTION

According to the novel by Mehdi Ghasemi, Mohammad Hussein Moaiyeri, Keivan Navi, published on Jan 10, 2012. Due to high power consumption and difficulties with minimizing the CMOS transistor size, molecular electronics has been introduced as an emerging technology. Further, there have been noticeable advances in fabrication of molecular wires and switches and also molecular diodes can be used for designing different logic circuits.

Considering their technology novel, they use molecules as the active components of the circuit, for transporting electric charge. They presented a full adder circuit based on molecular electronics. This full adder is consisted of resonant tunneling diodes and transistors which are implemented via molecular electronics. The area occupied by this kind of full adder would be much times smaller than the conventional designs and it can be used as the building block of more complex molecular arithmetic circuits.

Ramya Menon C. and Vinod Pangracious 16 Jan 2012 published a novel which declares that; in a multiprocessor system on chip (MPSOC) IC the processor is one of the highest heat dissipating devices. The temperature generated in an IC may vary with floor plan of the chip. The novel proposes an integration and thermal analysis methodology to extract the peak temperature and temperature distribution of 2-dimensional and 3-dimensional multiprocessor system-on-chip. As we know the peak temperature of chip increases in 3-dimensional structures compared to 2-dimensional ones due to the reduced space in intra-layer and inter-layer components.

In sub-nanometer scale technologies, it is inevitable to analyze the heat developed in individual chip to extract the temperature distribution of the entire chip. With the technology scaling in new generation ICs more and more components are integrated to a smaller area. Along with the other parameters threshold voltage is also scaled down which results in exponential increase in leakage current. This has resulted in rise in hotspot temperature value due to increase in leakage power. They analyzed the temperature developed in an IC with four identical processors at 2.4 GHz in different floor plans. The analysis has been done for both 2D and 3D arrangements. In the 3D arrangement, a three layered structure has been considered with two Silicon layers and a thermal interface material (TIM) in between them. Based on experimental results they propose a methodology to reduce the peak temperature developed in 2D and 3D integrated circuits.

  HISTORY

Until the late 1970’s, most minicomputer did not have a multiple instruction, and so programmers used a “multiply routine” which repeatedly shifts and accumulates partial results, often written using loop unwinding. Mainframe computers had multiply instructions. The Motorola 6809, introduced in 1978, was one of the earliest microprocessors with a dedicated hardware multiplying instruction. It did the same sorts of shifts and adds as a “multiply routine”, but implemented in the microcode of the MUL instruction [citation needed].

As more transistors per chip became available due to Larger Scale Integration (LSI), it become possible to put enough adders on a single chip to sum all the partial products at once, rather than reuse a single adder to handle each partial product one at a time. Because common digital signal processing algorithms spend most of their time on multiplying, digital signal processor designers sacrifice a lot of chip area in order to make the multiply-accumulate unit often used up most of the chip area of early DSPs.

     RESEARCH METHODOLOGY

     SIMILAR WORKS BASED ON FULL ADDER CIRCUITS

Some designs of adder cells can be found in the figures 1 to 6. These six different adder cells are simulated in 0.18 µm CMOS technology and tested separately. All these cells are optimum in power dissipation and Power delay product (PDP). The conventional adder shown in figure 1 is implemented with 28 Transistors in CMOS technology. Conventional adder circuits do not function well below one volt supply. Figure 2 shows the Complementary Pass-transistor Logic (CPL) adder. Among the pass transistor logic styles, CPL has the best performance and the lowest power delay product.

The Transmission Function full Adder (TFA), which is shown in figure 3, uses 16 transistors. Pull-up and pull-down logic is used to drive the load the same as the complementary pass logic. Figure 4 shows the Transmission Gate full adder (TG). TG adder includes 20 transistors, and generates a+b and its complement to produce the sum and carry signals. It uses complementary input signals (a, b, c) as the complementary CMOS full adder. This full adder uses only 14 transistors to make the adder function. The circuit occupies less area in comparison with other CMOS full adder cells. At end, another full adder with 26 transistors is presented in figure 6.

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